1. Field of the Invention
The present invention relates to a semiconductor memory having a mode register that sets an operation mode and a system apparatus having the semiconductor memory mounted thereon.
2. Description of the Related Art
In general, a semiconductor memory such as a DRAM has a power-on reset circuit. An internal circuit such as a latch is initialized by a power-on reset signal generated when a power supply voltage is low. A method of resetting a test mode register in response to both the power-on reset signal and an initialize command (precharge command) supplied from outside is disclosed in Japanese Unexamined Patent Application Publication No. 11-149771.
In a case in which an internal circuit such as the test mode register is directly reset by the initialize command supplied from outside, when a typical write command is recognized incorrectly as an initialize command due to noise and so on, the internal circuit is reset. In addition, when a user employs a command (e.g. a precharge command) used to operate a semiconductor memory for the initialize command, a chance increases that the user (system) supplies the initialize command to the semiconductor memory incorrectly, which causes a problem in that an unexpected command may reset the internal circuit.